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PRELIMINARY
80960MC
EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT
Commercial
s High-Performance Embedded Architecture s On-Chip Memory Management Unit
-- 25 MIPS Burst Execution at 25 MHz -- 9.4 MIPS* Sustained Execution at 25 MHz s On-Chip Floating Point Unit -- Supports IEEE 754 Floating Point Standard -- Full Transcendental Support -- Four 80-Bit Registers -- 13.6 Million Whetstones/s (Single Precision) at 25 MHz s 512-Byte On-Chip Instruction Cache -- Direct Mapped -- Parallel Load/Decode for Uncached Instructions s Multiple Register Sets -- Sixteen Global 32-Bit Registers -- Sixteen Local 32-Bit Registers -- Four Local Register Sets Stored On-Chip (Sixteen 32-Bit Registers per Set) -- Register Scoreboarding
s
s
s
s
-- 4 Gbyte Virtual Address Space per Task -- 4 Kbyte Pages with Supervisor/User Protection Built-in Interrupt Controller -- 32 Priority Levels -- 248 Vectors -- Supports M8259A -- 3.4 s Latency @ 25 MHz Easy to Use, High Bandwidth 32-Bit Bus -- 66.7 Mbytes/s Burst -- Up to 16 Bytes Transferred per Burst Multitasking and Multiprocessor Support -- Automatic Task dispatching -- Prioritized Task Queues Advanced Package Technology -- 132-Lead Ceramic Pin Grid Array
FOUR 80-BIT FP REGISTERS 80-BIT FPU
SIXTEEN 32-BIT GLOBAL REGISTERS
64- BY 32-BIT LOCAL REGISTER CACHE
32-BIT INSTRUCTION EXECUTION UNIT
MMU
32-BIT BUS CONTROL LOGIC INSTRUCTION FETCH UNIT 512-BYTE INSTRUCTION CACHE INSTRUCTION DECODER MICROINSTRUCTION SEQUENCER MICROINSTRUCTION ROM 32-BIT BURST BUS
Figure 1. The 80960MC Processor's Highly Parallel Architecture (c) INTEL CORPORATION, 1997 September, 1997 Order Number: 273123-001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-7641 or call 1-800-879-4683 Many documents are available for download from Intel's website at http://www.intel.com Copyright (c) Intel Corporation 1997
80960MC
1.0 THE i960(R) MC PROCESSOR ................................................................................................................. .. 1 1.1 Key Performance Features ................................................................................................................. 2 1.1.1 Memory Space And Addressing Modes ................................................................................... 4 1.1.2 Data Types ............................................................................................................. .................. 4 1.1.3 Large Register Set ..................................................................................................... .............. 4 1.1.4 Multiple Register Sets .............................................................................................................. 5 1.1.5 Instruction Cache ..................................................................................................................... 5 1.1.6 Register Scoreboarding ................................................................................................. .......... 5 1.1.7 Memory Management and Protection ...................................................................................... 6 1.1.8 Floating-Point Arithmetic .............................................................................................. ............ 6 1.1.9 Multitasking Support ................................................................................................................ 7 1.1.10 Synchronization and Communication .................................................................................... 7 1.1.11 High Bandwidth Local Bus ..................................................................................................... 7 1.1.12 Multiple Processor Support .................................................................................................... 7 1.1.13 Interrupt Handling .................................................................................................... .............. 8 1.1.14 Debug Features ..................................................................................................................... 8 1.1.15 Fault Detection ....................................................................................................................... 8 1.1.16 Inter-Agent Communications (IAC) ........................................................................................ 9 1.1.17 Built-in Testability ................................................................................................................... 9 1.1.18 Compatibility with 80960K-Series ...................................................................................... .... 9 1.1.19 CHMOS .................................................................................................................................. 9 2.0 ELECTRICAL SPECIFICATIONS ................................................................................................ ........... 13 2.1 Power and Grounding ....................................................................................................................... 13 2.2 Power Decoupling Recommendations ......................................................................................... .... 13 2.3 Connection Recommendations ........................................................................................................ 13 2.4 Characteristic Curves ....................................................................................................................... 13 2.5 Test Load Circuit .............................................................................................................................. 16 2.7 DC Characteristics ............................................................................................................................ 17 2.6 Absolute Maximum Ratings .............................................................................................................. 17 2.8 AC Specifications ............................................................................................................................. 18 2.9 Design Considerations ..................................................................................................................... 22 3.0 MECHANICAL DATA .............................................................................................................................. 22 3.1 Packaging ......................................................................................................................................... 22 3.1.1 Pin Assignment ...................................................................................................................... 22 3.2 Pinout ............................................................................................................................................... 26 3.3 Package Thermal Specification ........................................................................................................ 28 4.0 WAVEFORMS ......................................................................................................................................... 30 5.0 REVISION HISTORY ............................................................................................................................... 35
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FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. 80960MC Instruction Set ........................................................................................................... 3 Memory Addressing Modes ....................................................................................................... 4 Sample Floating-Point Execution Times (s) at 25 MHz ........................................................... 7 80960MC Pin Description: L-Bus Signals .................................................................................. 9 80960MC Pin Description: Support Signals ............................................................................. 11 DC Characteristics ................................................................................................................... 17 80960MC AC Characteristics (25 MHz) ...................................................................................20 80960MC PGA Pinout -- In Pin Order .....................................................................................26 80960MC PGA Pinout -- In Signal Order ................................................................................ 27 80960MC PGA Package Thermal Characteristics ................................................................... 28 80960MC Programming Environment ........................................................................................ 1 Instruction Formats .................................................................................................................... 4 Multiple Register Sets Are Stored On-Chip ............................................................................... 6 Connection Recommendations for Low Current Drive Network .............................................. 13 Connection Recommendations for High Current Drive Network .............................................. 13 Typical Supply Current vs. Case Temperature ........................................................................ 14 Typical Current vs. Frequency (Room Temp) .......................................................................... 14 Typical Current vs. Frequency (Hot Temp) .............................................................................. 15 Worst-Case Voltage vs. Output Current on Open-Drain Pins .................................................. 15 Capacitive Derating Curve ....................................................................................................... 15 Test Load Circuit for Three-State Output Pins ......................................................................... 16 Test Load Circuit for Open-Drain Output Pins ......................................................................... 16 Drive Levels and Timing Relationships for 80960MC Signals ................................................. 18 Timing Relationship of L-Bus Signals ................................................................................ ...... 19 System and Processor Clock Relationship ............................................................................. . 19 Processor Clock Pulse (CLK2) ................................................................................................ 21 RESET Signal Timing .............................................................................................................. 21 HOLD Timing ........................................................................................................................... 22 132-Lead Pin-Grid Array (PGA) Package ................................................................................ 23 80960MC PGA Pinout--View from Bottom (Pins Facing Up) .................................................. 24 80960MC PGA Pinout--View from Top (Pins Facing Down) .................................................. 25 25 MHz Maximum Allowable Ambient Temperature ................................................................ 29 Non-Burst Read and Write Transactions Without Wait States ................................................. 30 Burst Read and Write Transaction Without Wait States .......................................................... 31 Burst Write Transaction with 2, 1, 1, 1 Wait States .................................................................. 32 Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States) ......................................................................... 33 Interrupt Acknowledge Transaction ......................................................................................... 34 Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master) ..... 35
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1.0
THE i960(R) MC PROCESSOR
The 80960MC, a member of Intel's i960(R) 32-bit processor family, is ideally suited for embedded applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960MC has a large register set, multiple parallel execution units and a high-bandwidth burst bus. Using advanced RISC technology, this processor is capable of execution rates in excess of 9.4 million instructions per second*. The 80960MC is well-suited for a wide range of applications including non-impact printers, I/O control and specialty instrumentation. The embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and networking. These types of applications require high integration, low power consumption, quick interrupt response times and
* Relative to Digital Equipment Corporation's VAX-11/780* at 1 MIPS
high performance. Since time to market is critical, embedded processors must be easy to use in both hardware and software designs. All members of the i960 processor family share a common core architecture which utilizes RISC technology so that, except for special functions, the family members are object-code compatible. Each new processor in the family adds its own special set of functions to the core to satisfy the needs of a specific application or range of applications in the embedded market. The 80960MC includes an integrated Floating Point Unit (FPU), a Memory Management Unit (MMU), multitasking support, and multiprocessor support. Two commercial members of the i960(R) family provide similar features: the 80960KB processor with integrated FPU and the 80960KA without floatingpoint.
0000 0000H
FFFF FFFFH
ADDRESS SPACE
ARCHITECTURALLY DEFINED DATA STRUCTURES
FETCH
LOAD
STORE
INSTRUCTION CACHE
INSTRUCTION STREAM
INSTRUCTION EXECUTION
SIXTEEN 32-BIT GLOBAL REGISTERS
g0 g15
PROCESSOR STATE REGISTERS INSTRUCTION POINTER ARITHMETIC CONTROLS PROCESS CONTROLS TRACE CONTROLS
REGISTER CACHE
SIXTEEN 32-BIT LOCAL REGISTERS
r0 r15
FOUR 80-BIT FLOATING POINT REGISTERS
CONTROL REGISTERS
Figure 1. 80960MC Programming Environment
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1.1
Key Performance Features
6.
The 80960 architecture is based on the most recent advances in microprocessor technology and is grounded in Intel's long experience in the design and manufacture of embedded microprocessors. Many features contribute to the 80960MC's exceptional performance: 1. Large Register Set. Having a large number of registers reduces the number of times that a processor needs to access memory. Modern compilers can take advantage of this feature to optimize execution speed. For maximum flexibility, the 80960MC provides thirty-two 32-bit registers. (See Figure 2.) Fast Instruction Execution. Simple functions make up the bulk of instructions in most programs so that execution speed can be improved by ensuring that these core instructions are executed as quickly as possible. The most frequently executed instructions such as register-register moves, add/subtract, logical operations and shifts execute in one to two cycles. (Table 1 contains a list of instructions.) Load/Store Architecture. One way to improve execution speed is to reduce the number of times that the processor must access memory to perform an operation. As with other processors based on RISC technology, the 80960MC has a Load/Store architecture. As such, only the LOAD and STORE instructions reference memory; all other instructions operate on registers. This type of architecture simplifies instruction decoding and is used in combination with other techniques to increase parallelism. Simple Instruction Formats. All instructions in the 80960MC are 32 bits long and must be aligned on word boundaries. This alignment makes it possible to eliminate the instruction alignment stage in the pipeline. To simplify the instruction decoder, there are only five instruction formats; each instruction uses only one format. (See Figure 3.) Overlapped Instruction Execution. Load operations allow execution of subsequent instructions to continue before the data has been returned from memory, so that these instructions can overlap the load. The 80960MC manages this process transparently to software through the use of a register scoreboard. Conditional instructions also make use of a scoreboard so that subsequent unrelated instructions may be executed while the conditional instruction is pending. 7.
2.
8.
3.
Integer Execution Optimization. When the result of an arithmetic execution is used as an operand in a subsequent calculation, the value is sent immediately to its destination register. Yet at the same time, the value is put on a bypass path to the ALU, thereby saving the time that otherwise would be required to retrieve the value for the next operation. Bandwidth Optimizations. The 80960MC gets optimal use of its memory bus bandwidth because the bus is tuned for use with the onchip instruction cache: instruction cache line size matches the maximum burst size for instruction fetches. The 80960MC automatically fetches four words in a burst and stores them directly in the cache. Due to the size of the cache and the fact that it is continually filled in anticipation of needed instructions in the program flow, the 80960MC is relatively insensitive to memory wait states. The benefit is that the 80960MC delivers outstanding performance even with a low cost memory system. Cache Bypass. When a cache miss occurs, the processor fetches the needed instruction then sends it on to the instruction decoder at the same time it updates the cache. Thus, no extra time is spent to load and read the cache.
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5.
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Table 1. 80960MC Instruction Set Data Movement Load Store Move Load Address Load Physical Address Process Management Schedule Process Saves Process Resume Process Load Process Time Modify Process Controls Wait Conditional Wait Signal Receive Conditional Receive Send Send Service Atomic Add Atomic Modify Floating Point Add Subtract Multiply Divide Remainder Scale Round Square Root Sine Cosine Tangent Arctangent Log Log Binary Log Natural Exponent Classify Copy Real Extended Compare Bit and Bit Field Set Bit Clear Bit Not Bit Check Bit Alter Bit Scan For Bit Scan Over Bit Extract Modify Call/Return Call Call Extended Call System Return Branch and Link Logical And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Rotate
Comparison
Branch
String Move String Move Quick String Fill String Compare String Scan Byte for Equal
Compare Unconditional Branch Conditional Compare Conditional Branch Compare and Increment Compare and Branch Compare and Decrement
Conversion Convert Real to Integer Convert Integer to Real
Decimal Move Add with Carry Subtract with Carry
Arithmetic Add Subtract Multiply Divide Remainder Modulo Shift
Fault Conditional Fault Synchronize Faults
Debug Modify Trace Controls Mark Force Mark
Miscellaneous Flush Local Registers Inspect Access Modify Arithmetic Controls Test Condition Code
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Control
Opcode
Displacement
Compare and Branch
Opcode
Reg/Lit
Reg
M
Displacement
Register to Register
Opcode
Reg
Reg/Lit
Modes
Ext'd Op
Reg/Lit
Memory AccessShort
Opcode
Reg
Base
M
X
Offset
Memory AccessLong
Opcode
Reg
Base
Mode
Scale
xx
Offset
Displacement
Figure 2. Instruction Formats
1.1.1
Memory Space And Addressing Modes
1.1.2
Data Types
The 80960MC allows each task (process) to address a logical memory space of up to 4 Gbytes. Each task's address space is divided into four 1 Gbyte regions and each region can be mapped to physical addresses by zero, one, or two levels of page tables. The region with the highest addresses (Region 3) is common to all tasks. In keeping with RISC design principles, the number of addressing modes is minimal yet includes all those necessary to ensure efficient execution of high-level languages such as Ada, C, and Fortran. Table 2 lists the memory accessing modes. Table 2. Memory Addressing Modes * 12-Bit Offset * 32-Bit Offset * Register-Indirect * Register + 12-Bit Offset * Register + 32-Bit Offset * Register + (Index-Register x Scale-Factor) * Register x Scale Factor + 32-Bit Displacement * Register + (Index-Register x Scale-Factor) + 32Bit Displacement * Scale-Factor is 1, 2, 4, 8 or 16
The 80960MC recognizes the following data types: Numeric: * 8-, 16-, 32- and 64-bit ordinals * 8-, 16-, 32- and 64-bit integers * 32-, 64- and 80-bit real numbers Non-Numeric: * Bit * Bit Field * Triple Word (96 bits) * Quad-Word (128 bits) 1.1.3 Large Register Set
The 80960MC programming environment includes a large number of registers. 36 registers are available at any time; this greatly reduces the number of memory accesses required to perform algorithms, which leads to greater instruction processing speed. Two types of general-purpose registers are available: local and global. The 20 global registers consist of sixteen 32-bit registers (G0 though G15) and four 80-bit registers (FP0 through FP3). These
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80960MC
registers perform the same function as the generalpurpose registers provided in other popular microprocessors. The term global refers to the fact that these registers retain their contents across procedure calls. The local registers are procedure-specific. For each procedure call, the 80960MC allocates 16 local registers (R0 through R15). Each local register is 32 bits wide. Any register can also be used for floatingpoint operations; the 80-bit floating-point registers are provided for extended precision. 1.1.4 Multiple Register Sets
cache, the number of memory references required to read instructions into the processor is greatly reduced. To load the instruction cache, instructions are fetched in 16-byte blocks; up to four instructions can be fetched at one time. An efficient prefetch algorithm increases the probability that an instruction is already in the cache when it is needed. Code for small loops often fits entirely within the cache, leading to an increase in processing speed since further memory references might not be necessary until the program exits the loop. Similarly, when calling short procedures, the code for the calling procedure is likely to remain in the cache so it is there on the procedure's return. 1.1.6 Register Scoreboarding
To further increase the efficiency of the register set, multiple sets of local registers are stored on-chip (See Figure 4). This cache holds up to four local register frames, which means that up to three procedure calls can be made without having to access the procedure stack resident in memory. Although programs may have procedure calls nested many calls deep, a program typically oscillates back and forth between only two to three levels. As a result, with four stack frames in the cache, the probability of having a free frame available on the cache when a call is made is very high. Runs of representative C-language programs show that 80% of the calls are handled without needing to access memory. When four or more procedures are active and a new procedure is called, the 80960MC moves the oldest local register set in the stack-frame cache to a procedure stack in memory to make room for a new set of registers. Global register G15 is the frame pointer (FP) to the procedure stack. Global registers are not exchanged on a procedure call, but retain their contents, making them available to all procedures for fast parameter passing. 1.1.5 Instruction Cache
The instruction decoder is optimized in several ways. One optimization method is the ability to overlap instructions by using register scoreboarding. Register scoreboarding occurs when a LOAD moves a variable from memory into a register. When the instruction initiates, a scoreboard bit on the target register is set. Once the register is loaded, the bit is reset. In between, any reference to the register contents is accompanied by a test of the scoreboard bit to ensure that the load has completed before processing continues. Since the processor does not need to wait for the LOAD to complete, it can execute additional instructions placed between the LOAD and the instruction that uses the register contents, as shown in the following example: ld data_2, r4 ld data_2, r5 Unrelated instruction Unrelated instruction add R4, R5, R6 In essence, the two unrelated instructions between LOAD and ADD are executed "for free" (i.e., take no apparent time to execute) because they are executed while the register is being loaded. Up to three load instructions can be pending at one time with three corresponding scoreboard bits set. By exploiting this feature, system programmers and compiler writers have a useful tool for optimizing execution speed.
To further reduce memory accesses, the 80960MC includes a 512-byte on-chip instruction cache. The instruction cache is based on the concept of locality of reference; most programs are typically not executed in a steady stream but consist of many branches, loops and procedure calls that lead to jumping back and forth in the same small section of code. Thus, by maintaining a block of instructions in
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ONE OF FOUR LOCAL REGISTER SETS
REGISTER CACHE
LOCAL REGISTER SET
R0
31
0
R15
Figure 3. Multiple Register Sets Are Stored On-Chip
1.1.7
Memory Management and Protection
1.1.8
Floating-Point Arithmetic
The 80960MC is ideal for multitasking applications that require software protection and a large address space. To ensure the highest level of performance possible, the memory management unit (MMU) and translation look-aside buffer (TLB) are contained onchip. The 80960MC supports a conventional form of demand-paged virtual memory in which the address space is divided into 4-Kbyte pages. Studies indicate that a 4-Kbyte page is the optimum size for a broad range of applications. Each page table entry includes a 2-bit page rights field that specifies whether the page is a no-access, read-only, or read-write page. This field is interpreted differently depending on whether the current task (process) is executing in user or supervisor mode, as shown below: Rights 00 01 10 11 User No Access No Access Read-Only Read-Write Supervisor Read-Only Read-Write Read-Write Read-Write
In the 80960MC, floating-point arithmetic is an integral part of the architecture. Having the floatingpoint unit integrated on-chip provides two advantages. First, it improves the performance of the chip for floating-point applications, since no additional bus overhead is associated with floating-point calculations, thereby leaving more time for other bus operations such as I/O. Second, the cost of using floating-point operations is reduced because a separate coprocessor chip is not required. The 80960MC floating-point (real-number) data types include single-precision (32-bit), double-precision (64-bit) and extended precision (80-bit) floatingpoint numbers. Any registers may be used to execute floating-point operations. The processor provides hardware support for both mandatory and recommended portions of IEEE Standard 754 for floating-point arithmetic, including all arithmetic, exponential, logarithmic and other transcendental functions. Table 3 shows execution times for some representative instructions.
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Table 3. Sample Floating-Point Execution Times (s) at 25 MHz Function Add Subtract Multiply Divide Square Root Arctangent Exponent Sine Cosine 1.1.9 32-Bit 0.4 0.4 0.7 1.3 3.7 10.1 11.3 15.2 15.2 64-Bit 0.5 0.5 1.3 2.9 3.9 13.1 12.5 16.6 16.6
information by means of communication ports is asynchronous and automatically buffered by the processor. Communication between tasks by means of ports can be carried out independently of the operating system. Once the ports have been set up by the programmer, the processor handles the message passing automatically. 1.1.11 High Bandwidth Local Bus The 80960MC CPU resides on a high-bandwidth address/data bus known as the local bus (L-Bus). The L-Bus provides a direct communication path between the processor and the memory and I/O subsystem interfaces. The processor uses the L-Bus to fetch instructions, manipulate memory and respond to interrupts. L-Bus features include: * 32-bit multiplexed address/data path * Four-word burst capability which allows transfers from 1 to 16 bytes at a time * High bandwidth reads and writes with 66.7 MBytes/s burst (at 25 MHz) * Special signal to indicate whether a memory transaction can be cached Table 4 defines L-bus signal names and functions; Table 5 defines other component-support signals such as interrupt lines. 1.1.12 Multiple Processor Support One means of increasing the processing power of a system is to run two or more processors in parallel. Since microprocessors are not generally designed to run in tandem with other processors, designing such a system is usually difficult and costly. The 80960MC solves this problem by offering a number of functions to coordinate the actions of multiple processors. First, messages can be passed between processors to initiate actions such as flushing a cache, stopping or starting another processor, or preempting a task. The messages are passed on the bus and allow multiple processors to run together smoothly, with rare need to lock the bus or memory.
Multitasking Support
Multitasking programs commonly involve the monitoring and control of an external operation, such as the activities of a process controller or the movements of a machine tool. These programs generally consist of a number of processes that run independently of one another, but share a common database or pass data among themselves. The 80960MC offers several hardware functions designed to support multitasking systems. One unique feature, called self-dispatching, allows a processor to switch itself automatically among scheduled tasks. When self-dispatching is used, all the operating system is required to do is place the task in the scheduling queue. When the processor becomes available, it dispatches the task from the beginning of the queue and then executes it until it becomes blocked, interrupted, or until its time-slice expires. It then returns the task to the end of the queue (i.e., automatically reschedules it) and dispatches the next ready task. During these operations, no communication between the processor and the operating system is necessary until the running task is complete or an interrupt is issued. 1.1.10 Synchronization and Communication The 80960MC also offers instructions to set up and test semaphores to ensure that concurrent tasks remain synchronized and no data inconsistency results. Special data structures, known as communication ports, provide the means for exchanging parameters and data structures. Transmission of
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Second, a set of synchronization instructions help maintain memory coherency. These instructions permit several processors to modify memory at the same time without inserting inaccuracies or ambiguities into shared data structures. The self-dispatching mechanism -- in addition to being used in single-processor systems -- provides the means to increase the performance of a system merely by adding processors. Each processor can either work on the same pool of tasks (sharing the same queue with other processors) or can be restricted to its own queue. When processors perform system operation, they synchronize themselves by using atomic operations and sending special messages between each other. In theory, changing the number of processors in a system does not require a software change. Software executes correctly regardless of the number of processors in the system; systems with more processors simply execute faster. 1.1.13 Interrupt Handling The 80960MC can be interrupted in two ways: by the activation of one of four interrupt pins or by sending a message on the processor's data bus. The 80960MC is unusual in that it automatically handles interrupts on a priority basis and can keep track of pending interrupts through its on-chip interrupt controller. Two of the interrupt pins can be configured to provide 8259A-style handshaking for expansion beyond four interrupt lines. An interrupt message is made up of a vector number and an interrupt priority. When the interrupt priority is greater than that of the currently running task, the processor accepts the interrupt and uses the vector as an index into the interrupt table. When the priority of the interrupt message is below that of the current task, the processor saves the information in a section of the interrupt table reserved for pending interrupts. 1.1.14 Debug Features The 80960MC has built-in debug capabilities, including two types of breakpoints and six trace modes. Debug features are controlled by two internal 32-bit registers: the Process-Controls Word and the Trace-Controls Word. By setting bits in these
control words, a software debug monitor can closely control how the processor responds during program execution. The 80960MC has both hardware and software breakpoints. It provides two hardware breakpoint registers on-chip which, by using a special command, can be set to any value. When the instruction pointer matches either breakpoint register value, the breakpoint handling routine is automatically called. The 80960MC also provides software breakpoints through the use of two instructions: MARK and FMARK. These can be placed at any point in a program and cause the processor to halt execution at that point and call the breakpoint handling routine. The breakpoint mechanism is easy to use and provides a powerful debugging tool. Tracing is available for instructions (single step execution), calls and returns and branching. Each trace type may be enabled separately by a special debug instruction. In each case, the 80960MC executes the instruction first and then calls a trace handling routine (usually part of a software debug monitor). Further program execution is halted until the routine completes, at which time execution resumes at the next instruction. The 80960MC'S tracing mechanisms, implemented completely in hardware, greatly simplify the task of software test and debug. 1.1.15 Fault Detection The 80960MC has an automatic mechanism to handle faults. There are ten fault types include floating point, trace and arithmetic faults. When the processor detects a fault, it automatically calls the appropriate fault handling routine and saves the current instruction pointer and necessary state information to make efficient recovery possible. The processor posts diagnostic information on the type of fault to a Fault Record. Like interrupt handling routines, fault handling routines are usually written to meet the needs of specific applications and are often included as part of the operating system or kernel. For each of the ten fault types, numerous subtypes provide specific information about a fault. For example, a floating point fault may have the subtype set to an Overflow or Zero-Divide fault. The fault handler can use this specific information to respond correctly to the fault.
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1.1.16 Inter-Agent Communications (IAC) To coordinate their actions, processors in a multiple processor system need a means for communicating with each other. The 80960MC does this through a mechanism known as "IACs" -- Inter-Agent Communication messages. IAC messages cause a variety of actions including starting and stopping processors, flushing instruction caches and TLBs, and sending interrupts to other processors in the system. The upper 16 Mbytes of the processor's physical memory space is reserved for sending and receiving IAC messages. 1.1.17 Built-in Testability Upon reset, the 80960MC automatically conducts an exhaustive internal test of its major blocks of logic. Then, before executing its first instruction, it does a zero check sum on the first eight words in memory to ensure that the memory image was programmed correctly. When a problem is discovered at any point during the self-test, the 80960MC asserts its FAILURE pin and does not begin program execution. Self test takes approximately 47,000 cycles to complete.
System manufacturers can use the 80960MC's selftest feature during incoming parts inspection. No special diagnostic programs need to be written. The test is both thorough and fast. The self-test capability helps ensure that defective parts are discovered before systems are shipped and, once in the field, the self-test makes it easier to distinguish between problems caused by processor failure and problems resulting from other causes. 1.1.18 Compatibility with 80960K-Series Application programs written for the 80960K-Series microprocessors can be run on the 80960MC without modification. The 80960K-Series instruction set forms the core of the 80960MC's instructions, so binary compatibility is assured. 1.1.19 CHMOS The 80960MC is fabricated using Intel's CHMOS IV (Complementary High Speed Metal Oxide Semiconductor) process. The 80960MC is currently available at 25 MHz.
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 1 of 3) NAME CLK2 TYPE I DESCRIPTION SYSTEM CLOCK provides the fundamental timing for 80960MC systems. It is divided by two inside the 80960MC to generate the internal processor clock. Refer to Figure 16, Processor Clock Pulse (CLK2) (pg. 21) LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and from memory. During an address (Ta) cycle, bits 2-31 contain a physical word address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, bits 0-31 contain read or write data. These pins float to a high impedance state when not active. Bits 0-1 comprise SIZE during a Ta cycle. SIZE specifies burst transfer size in words. LAD1 0 0 1 1 ALE O T.S. LAD0 0 1 0 1 1 Word 2 Words 3 Words 4 Words
LAD31:0
I/O T.S.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is asserted during a Ta cycle and deasserted before the beginning of the Td state. It is active LOW and floats to a high impedance state during a hold cycle (Th).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
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9
80960MC
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 2 of 3) NAME ADS TYPE O O.D. O O.D. O O.D. DESCRIPTION ADDRESS/DATA STATUS indicates an address state. ADS is asserted every Ta state and deasserted during the following Td state. For a burst transaction, ADS is asserted again every Td state where READY was asserted in the previous cycle. WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read. It is latched on-chip and remains valid during Td cycles. DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the L-Bus. It is low during Ta and Td cycles for a read or interrupt acknowledgment; it is high during Ta and Td cycles for a write. DT/R never changes state when DEN is asserted. DATA ENABLE (active low) enables data transceivers. The processor asserts DEN# during all Td and Tw states. The DEN# line is an open drain-output of the 80960MC. READY indicates that data on LAD lines can be sampled or removed. When READY is not asserted during a Td cycle, the Td cycle is extended to the next cycle by inserting a wait state (Tw ) and ADS is not asserted in the next cycle. BUS LOCK prevents bus masters from gaining control of the L-Bus during Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert LOCK. At the start of a RMW operation, the processor examines the LOCK pin. When the pin is already asserted, the processor waits until it is not asserted. When the pin is not asserted, the processor asserts LOCK during the Ta cycle of the read transaction. The processor deasserts LOCK in the Ta cycle of the write transaction. During the time LOCK is asserted, a bus agent can perform a normal read or write but not a RMW operation. The processor also asserts LOCK during interrupt-acknowledge transactions. Do not leave LOCK unconnected. It must be pulled high for the processor to function properly. BE3:0 O O.D. BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are used in the current bus cycle. BE3 corresponds to LAD31:24; BE0 corresponds to LAD7:0. The byte enables are provided in advance of data: Byte enables asserted during Ta specify the bytes of the first data word. Byte enables asserted during Td specify the bytes of the next data word, if any (the word to be transmitted following the next assertion of READY). Byte enables that occur during Td cycles that precede the last assertion of READY are undefined. Byte enables are latched on-chip and remain constant from one Td cycle to the next when READY is not asserted. For reads, byte enables specify the byte(s) that the processor actually uses. L-Bus agents are required to assert only adjacent byte enables (e.g., asserting just BE0 and BE2 is not permitted) and are required to assert at least one byte enable. Address bits A0 and A1 can be decoded externally from the byte enables. I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
W/R DT/R
DEN
O O.D. I
READY
LOCK
I/O O.D.
10
PRELIMINARY
80960MC
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 3 of 3) NAME HOLD/ HLDAR TYPE I DESCRIPTION HOLD: A request from an external bus master to acquire the bus. When the processor receives HOLD and grants bus control to another master, it floats its three-state bus lines and open-drain control lines, asserts HLDA and enters the Th state. When HOLD deasserts, the processor deasserts HLDA and enters the Ti or Ta state. HOLD ACKNOWLEDGE RECEIVED: Indicates that the processor has acquired the bus. When the processor is initialized as the secondary bus master this input is interpreted as HLDAR. Refer to Figure 18, HOLD Timing (pg. 22). HLDA/ HOLDR O T.S. HOLD ACKNOWLEDGE: Relinquishes control of the bus to another bus master. When the processor is initialized as the primary bus master this output is interpreted as HLDA. When HOLD is deasserted, the processor deasserts HLDA and goes to either the Ti or Ta state. HOLD REQUEST: Indicates a request to acquire the bus. When the processor is initialized as the secondary bus master this output is interpreted as HOLDR. Refer to Figure 18, HOLD Timing (pg. 22). CACHE/ TAG O T.S. CACHE indicates when an access is cacheable during a Ta cycle. It is not asserted during any synchronous access, such as a synchronous load or move instruction used for sending an IAC message. The CACHE signal floats to a high impedance state when the processor is idle. TAG is an input/output signal that, during Td and Tw cycles, identifies the contents of a 32-bit word as either data (TAG = 0) or an access descriptor (TAG = 1). I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state Table 5. 80960MC Pin Description: Support Signals (Sheet 1 of 2) NAME BADAC TYPE I DESCRIPTION BAD ACCESS, when asserted in the cycle following the one in which the last READY of a transaction is asserted, indicates that an unrecoverable error has occurred on the current bus transaction or that a synchronous load/store instruction has not been acknowledged. During system reset the BADAC signal is interpreted differently. When the signal is high, it indicates that this processor will perform system initialization. When low, another processor in the system will perform system initialization instead. RESET I RESET clears the processor's internal logic and causes it to reinitialize. During RESET assertion, the input pins are ignored (except for BADAC and IAC/INT0), the three-state output pins are placed in a high impedance state and other output pins are placed in their non-asserted states. RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET. The HIGH to LOW transition of RESET should occur after the rising edge of both CLK2 and the external bus clock and before the next rising edge of CLK2. Refer to Figure 17, RESET Signal Timing (pg. 21). I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
PRELIMINARY
11
80960MC
Table 5. 80960MC Pin Description: Support Signals (Sheet 2 of 2) NAME FAILURE TYPE O O.D. DESCRIPTION INITIALIZATION FAILURE indicates that the processor did not initialize correctly. After RESET deasserts and before the first bus transaction begins, FAILURE asserts while the processor performs a self-test. When the self-test completes successfully, then FAILURE deasserts. The processor then performs a zero checksum on the first eight words of memory. When it fails, FAILURE asserts for a second time and remains asserted. When it passes, system initialization continues and FAILURE remains deasserted. INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC message or an interrupt is pending. The bus interrupt control register determines how the signal is interpreted. To signal an interrupt or IAC request in a synchronous system, this pin -- as well as the other interrupt pins -- must be enabled by being deasserted for at least one bus cycle and then asserted for at least one additional bus cycle. In an asynchronous system the pin must remain deasserted for at least two bus cycles and then asserted for at least two more bus cycles. LOCAL PROCESSOR NUMBER - this signal is interpreted differently during system reset. When the signal is a high voltage level it indicates that this processor is a primary bus master (local processor number = 0). When at a low voltage level it indicates that this processor is a secondary bus master (local processor number = 1). INT1 INT2/INTR I I INTERRUPT 1, like INT0, provides direct interrupt signaling. INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines how this pin is interpreted. When INT2, it has the same interpretation as the INT0 and INT1 pins. When INTR, it is used to receive an interrupt request from an external interrupt controller. INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register determines how this pin is interpreted. When INT3, it has the same interpretation as the INT0, INT1 and INT2 pins. When INTA, it is used as an output to control interrupt-acknowledge transactions. The INTA output is latched on-chip and remains valid during Td cycles; as an output, it is open-drain. NOT CONNECTED indicates pins should not be connected. Never connect any pin marked N.C. as these pins may be reserved for factory use.
IAC/INT0 LOCAL PROCESSOR NUMBER
I
INT3/INTA
I/O O.D.
N.C.
N/A
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
12
PRELIMINARY
80960MC
2.0 2.1
ELECTRICAL SPECIFICATIONS Power and Grounding
NOTE: Do not connect external logic to pins marked N.C.
VCC OPEN-DRAIN OUTPUT 220
The 80960MC is implemented in CHMOS IV technology and therefore has modest power requirements. Its high clock frequency and numerous output buffers (address/data, control, error and arbitration signals) can cause power surges as multiple output buffers simultaneously drive new signal levels. For clean on-chip power distribution, VCC and VSS pins separately feed the device's functional units. Power and ground connections must be made to all 80960MC power and ground pins. On the circuit board, all Vcc pins must be strapped closely together, preferably on a power plane; all Vss pins should be strapped together, preferably on a ground plane.
Low Drive Network: VOH = 3.0 V IOL = 20.7 mA
330
Figure 4. Connection Recommendations for Low Current Drive Network
2.2
Power Decoupling Recommendations
VCC OPEN-DRAIN OUTPUT 180
Place a liberal amount of decoupling capacitance near the 80960MC. When driving the L-bus the processor can cause transient power surges, particularly when connected to a large capacitive load. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance is reduced by shortening board traces between the processor and decoupling capacitors as much as possible.
High Drive Network: VOH = 3.4 V IOL = 25.3 mA
390
Figure 5. Connection Recommendations for High Current Drive Network
2.3
Connection Recommendations
2.4
Characteristic Curves
For reliable operation, always connect unused inputs to an appropriate signal level. In particular, when one or more interrupt lines are not used, they should be pulled up. No inputs should ever be left floating. All open-drain outputs require a pull-up device. While in most cases a simple pull-up resistor is adequate, a network of pull-up and pull-down resistors biased to a valid VIH (>3.0 V) and terminated in the characteristic impedance of the circuit board is recommended to limit noise and AC power consumption. Figure 5 and Figure 6 show recommended values for the resistor network for low and high current drive, assuming a characteristic impedance of 100 . Terminating output signals in this fashion limits signal swing and reduces AC power consumption.
Figure 7 shows typical supply current requirements over the operating temperature range of the processor at supply voltage (VCC) of 5 V. Figure 8 and Figure 9 show the typical power supply current (ICC ) that the 80960MC requires at various operating frequencies when measured at three input voltage (VCC ) levels and two temperatures. For a given output current (IOL) the curve in Figure 10 shows the worst case output low voltage (VOL). Figure 11 shows the typical capacitive derating curve for the 80960MC measured from 1.5V on the system clock (CLK) to 1.5V on the falling edge and 1.5V on the rising edge of the L-Bus address/data (LAD) signals.
PRELIMINARY
13
80960MC
VCC = 5.0 V
380 360 340
POWER SUPPLY CURRENT (mA)
320 300 280 260 240 220 200 -60 -40 -20 0 20 40 60 80 100 120 140
25 MHz 20 MHz 16 MHz
CASE TEMPERATURE (C)
Figure 6. Typical Supply Current vs. Case Temperature
TEMP = +22C
400 380
@5.5V 360 @5.0V @4.5V TYPICAL SUPPLY CURRENT (mA) 340 320 300 280 260 240 220 200 180
16
20
25
OPERATING FREQUENCY (MHz)
Figure 7. Typical Current vs. Frequency (Room Temp)
14
PRELIMINARY
80960MC
TEMP = +22C
380 360
@5.5V 340 @5.0V @4.5V TYPICAL SUPPLY CURRENT (mA) 320 300 280 260 240 220 200 180 160
16
20
25
OPERATING FREQUENCY (MHz)
Figure 8. Typical Current vs. Frequency (Hot Temp)
(TEMP = +85C, VCC = 4.5V) OUTPUT LOW VOLTAGE (V)
(TEMP = +85C, VCC = 4.5V) 30
FALLING
THREE-STATE OUTPUT VALID DELAY(ns)
25 20 15 10 5 0 0 20 40 60 80 100 CAPACITIVE LOAD(pF)
RISING
0.8 0.6 0.4 0.2 0.0 0 10 20 30 40 50 OUTPUT LOW CURRENT(mA)
Figure 9. Worst-Case Voltage vs. Output Current on Open-Drain Pins
Figure 10. Capacitive Derating Curve
PRELIMINARY
15
80960MC
2.5
Test Load Circuit
THREE-STATE OUTPUT
Figure 12 illustrates the load circuit used to test the 80960MC's three-state pins; Figure 13 shows the load circuit used to test the open drain outputs. The open drain test uses an active load circuit in the form of a matched diode bridge. Since the open-drain outputs sink current, only the IOL legs of the bridge are necessary and the IOH legs are not used. When the 80960MC driver under test is turned off, the output pin is pulled up to VREF (i.e., VOH). Diode D1 is turned off and the IOL current source flows through diode D2. When the 80960MC open-drain driver under test is on, diode D1 is also on and the voltage on the pin being tested drops to VOL. Diode D2 turns off and IOL flows through diode D1.
CL
CL = 50 pF for all signals
Figure 11. Test Load Circuit for Three-State Output Pins
IOL OPEN-DRAIN OUTPUT D1 D2
CL
I OL Tested at 25 mA VREF = VCC D1 and D2 are matched
CL = 50 pF for all signals
Figure 12. Test Load Circuit for Open-Drain Output Pins
16
PRELIMINARY
80960MC
2.6
Absolute Maximum Ratings
0 C to +85 C Case -65 C to +150 C -0.5 V to VCC +0.5 V 2.5 W (25 MHz)
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temperature (PGA) ...... Storage Temperature..................... Voltage on Any Pin ........................ Power Dissipation ..........................
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
2.7
PGA:
DC Characteristics
80960MC (25 MHz) TCASE = 0 C to +85 C, VCC = 5V 5% Table 6. DC Characteristics
Symbol VIL VIH VCL VCH VOL VOH ICC
Parameter Input Low Voltage Input High Voltage CLK2 Input Low Voltage CLK2 Input High Voltage Output Low Voltage Output High Voltage Power Supply Current: 16 MHz 20 MHz 25 MHz Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance Clock Capacitance
Min -0.3 2.0 -0.3 0.55 VCC 2.4
Max +0.8 VCC + 0.3 +0.8 VCC + 0.3 0.45
Units V V V V V V
Notes
(1,2) (3,4) (5) (5) (5) 0 VIN VCC 0.45 VO VCC fC = 1 MHz (6) fC = 1 MHz (6) fC = 1 MHz (6)
315 360 420 15 15 10 12 10
mA mA mA A A pF pF pF
ILI ILO CIN CO CCLK
NOTES: 1. For three-state outputs, this parameter is measured at: Address/Data 4.0 mA Controls 5.0 mA 2. For open-drain outputs 25 mA 3. This parameter is measured at: Address/Data -1.0 mA Controls -0.9 mA -5.0 mA ALE 4. Not measured on open-drain outputs. 5. Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions in Figure 12 and Figure 13. Figure 7, Figure 8 and Figure 9 indicate typical values. 6. Input, output and clock capacitance are not tested.
PRELIMINARY
17
80960MC
2.8
AC Specifications
This section describes the AC specifications for the 80960MC pins. All input and output timings are specified relative to the 1.5 V level of the rising edge of CLK2. For output timings the specifications refer to the time it takes the signal to reach 1.5 V.
For input timings the specifications refer to the time at which the signal reaches (for input setup) or leaves (for hold time) the TTL levels of LOW (0.8 V) or HIGH (2.0 V). All AC testing should be done with input voltages of 0.4 V and 2.4 V, except for the clock (CLK2), which should be tested with input voltages of 0.45 V and 0.55 VCC.
EDGE
A
B
C
D
A
B
C
CLK2
0.8V
1.5V
1.5V
1.5V
1.5V
OUTPUTS: LAD 31:0 ADS W/R, DEN BE3:0 HLDA/HOLDR CACHE LOCK, INTA
T6
1.5V
T9
VALID OUTPUT 1.5V
T8
T8 T13
1.5V
T14
ALE
1.5V
T7 T6
DT/R
1.5V VALID OUTPUT
T9
1.5V
T10
INPUTS: LAD31:0 BADAC IAC/INT0, INT1 INT2/INTR, INT3 HOLD, HLDAR LOCK READY
2.0V 0.8V
T11
2.0V 0.8V
T12
2.0V 0.8V
T11
2.0V 0.8V
VALID INPUT
Figure 13. Drive Levels and Timing Relationships for 80960MC Signals
18
PRELIMINARY
80960MC
Ta T3 CLK2
T2
Td T1
Tr
Ta
Td
Td
Tr
CLK T6 LAD (31-0) ALE# T7 ADS# BE(0:3)# T13 W/R# T6 DT/R T6 DEN# T 14 T13
Address
T9
T10
Data
T11
T6
T13
Address T8
T6
Data T9
T9
T8 T14
T7
T9 T9
T13 T6
T14
T9
T6 T12 T11
READY#
T12 T11
T12 T11
A4484-01
Figure 14. Timing Relationship of L-Bus Signals
Bus State Ta CLK2 CLK
Bus State Td
Bus State Tr
Figure 15. System and Processor Clock Relationship
PRELIMINARY
19
80960MC
Table 7. 80960MC AC Characteristics (25 MHz) Symbol Parameter Min Max Units Notes
Input Clock T1 T2 T3 T4 T5 Processor Clock Period (CLK2) Processor Clock Low Time (CLK2) Processor Clock High Time (CLK2) Processor Clock Fall Time (CLK2) Processor Clock Rise Time (CLK2) 20 5 5 10 10 125 ns ns ns ns ns VIN = 1.5V VIL = 10% Point = 1.2V VIH = 90% Point = 0.1V + 0.5 VCC VIN = 90% Point to 10% Point (1) VIN = 10% Point to 90% Point (1)
Synchronous Outputs T6 T6H T7 T8 T9 T9H Output Valid Delay HLDA Output Valid Delay ALE Width ALE Output Valid Delay Output Float Delay HLDA Output Float Delay 2 4 12 2 2 4 18 18 20 18 23 ns ns ns ns ns ns (2) (2)
Synchronous Inputs T10 T11 T11H T12 T13 T14 T15 T16 T17
NOTES: 1. Clock rise and fall times are not tested. 2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested; however, it should not be longer than the valid delay. 3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT0, INT1, INT2/INTR and INT3 may be synchronous or asynchronous.
Input Setup 1 Input Hold HOLD Input Hold Input Setup 2 Setup to ALE Inactive Hold after ALE Inactive Reset Hold Reset Setup Reset Width
3 5 4 7 8 8 3 5 820
ns ns ns ns ns ns ns ns ns
(3) (3)
41 CLK2 Periods Minimum
20
PRELIMINARY
80960MC
T1 T3
HIGH LEVEL (MIN) 0.55VCC
90%
1.5 V
LOW LEVEL (MAX) 0.8V
10% T5 T4 T2
Figure 16. Processor Clock Pulse (CLK2)
CLK2
CLK
RESET
... ... ...
T17
FIRST ABC
D
A
T15 T16
OUTPUTS
...
T15 = RESET HOLD T16 = RESET SETUP T17 = RESET WIDTH
INIT PARAMETERS (BADAC, INT0/IAC) MUST BE SET UP 8 CLOCKS PRIOR TO THIS CLK2 EDGE INIT PARAMETERS MUST BE HELD BEYOND THIS CLK2 EDGE
Figure 17. RESET Signal Timing
PRELIMINARY
21
80960MC
Th CLK2
Th
Th
Th
CLK T6h HOLDR T12 HOLD T6h HLDA T12 HLDAR T11h T9h T11h T 9h
Primary HOLD HLDA D D
Secondary HOLDR HOLDAR
Delay of 5 ns Minimum is Required
A4490-01
Figure 18. HOLD Timing
2.9
Design Considerations
3.0 3.1
MECHANICAL DATA Packaging
Input hold times can be disregarded by the designer whenever the input is removed because a subsequent output from the processor is deasserted (e.g., DEN becomes deasserted). In other words, whenever the processor generates an output that indicates a transition into a subsequent state, the processor must have sampled any inputs for the previous state. Similarly, whenever the processor generates an output that indicates a transition into a subsequent state, any outputs that are specified to be three stated in this new state are guaranteed to be three stated.
The 80960MC is available in one package type: a 132-lead ceramic pin-grid array (PGA). Pins are arranged 0.100 inch (2.54 mm) center-to-center, in a 14 by 14 matrix, three rows around (see Figure 20). Dimensions for the PGA package type is given in the Intel Packaging handbook (Order #240800). 3.1.1 Pin Assignment
Figure 21 shows the view from the PGA bottom (pins facing up). Table 8 and Table 9 list the function of each PGA pin.
22
PRELIMINARY
80960MC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 ABCD E FGH J K LMN P
Figure 19. 132-Lead Pin-Grid Array (PGA) Package
PRELIMINARY
23
80960MC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P VCC N VSS M N.C. L DEN K BE3 J DT/R H W/R G LAD30 READY BE1 F LAD29 LAD31 CACHE E LAD28 LAD26 LAD27 D ALE C HOLD LAD25 BADAC VCC VSS LAD20 LAD13 LAD8 LAD3 VCC B LAD23 LAD24 LAD22 LAD21 LAD18 LAD15 LAD12 LAD10 LAD6 LAD2 CLK2 LAD0 RESET VSS A VCC VSS LAD19 LAD17 LAD 16 LAD14 LAD11 LAD9 LAD7 LAD5 LAD4 LAD1 INT2 VCC VSS INT3 INT1 INT0 ADS HLDA VCC N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. BE0 LOCK N.C. N.C. N.C. BE2 VSS N.C. N.C. N.C. FAIL VSS VCC N.C. N.C. N.C. VCC VSS N.C. N.C. VCC VSS VSS VCC N.C. N.C. N.C. N.C. VSS VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VCC
P
N M L K J H G F E D C B A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 20. 80960MC PGA Pinout--View from Bottom (Pins Facing Up)
24
PRELIMINARY
80960MC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P VCC N N.C. M N.C. L N.C. K J N.C. H N.C. G N.C. F N.C. E N.C. D N.C. C INT0 B VSS RESET LAD0 CLK2 LAD2 LAD6 LAD10 LAD12 LAD15 LAD18 LAD21 LAD 22 LAD24 LAD23 A VCC INT2 LAD1 LAD4 LAD5 LAD7 LAD9 LAD11 LAD14 LAD16 LAD17 LAD 19 VSS VCC INT1 INT3 VSS VCC LAD3 LAD8 LAD13 LAD20 VSS VCC BADAC LAD25 HOLD N.C. VCC HLDA ADS ALE VSS N.C. LAD27 LAD26 LAD28 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VCC N.C. FAIL BE2 BE0 DEN N.C. N.C. VCC VSS N.C. N.C. N.C. N.C. VCC VSS VSS VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VCC VSS
P
N M L K
A80960MC-25
VCC
VSS VSS
BE3 J DT/R H W/R G
XXXXXXXX XXXXXX XXXXXX
LOCK
BE1 READY LAD30 F CACHE LAD31 LAD29 E D C B A
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 21. 80960MC PGA Pinout--View from Top (Pins Facing Down)
PRELIMINARY
25
80960MC
3.2
Pinout
Table 8. 80960MC PGA Pinout -- In Pin Order
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5
Signal VCC V SS LAD19 LAD17 LAD16 LAD14 LAD11 LAD9 LAD7 LAD5 LAD4 LAD1 INT2/INTR VCC LAD23 LAD24 LAD22 LAD21 LAD18 LAD15 LAD12 LAD10 LAD6 LAD2 CLK2 LAD0 RESET VSS HOLD/HLDAR LAD25 BADAC VCC V SS
Pin C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D12 D13 D14 E1 E2 E3 E12 E13 E14 F1 F2 F3 F12 F13 F14 G1 G2 G3 G12 G13 G14
Signal LAD20 LAD13 LAD8 LAD3 VCC VSS INT3/INTA INT1 IAC/INT0 ALE ADS HLDA/HOLDR VCC N.C. N.C. LAD28 LAD26 LAD27 N.C. VSS N.C. LAD29 LAD31 CACHE/TAG N.C. N.C. N.C. LAD30 READY BE1 N.C. N.C. N.C.
Pin H1 H2 H3 H12 H13 H14 J1 J2 J3 J12 J13 J14 K1 K2 K3 K12 K13 K14 L1 L2 L3 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9
Signal W/R BE0 LOCK N.C. N.C. N.C. DT/R BE 2 VSS N.C. N.C. N.C. BE3 FAILURE VSS VCC N.C. N.C. DEN N.C. VCC VSS N.C. N.C. N.C. VCC VSS VSS VCC N.C. N.C. N.C. N.C.
Pin M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
Signal VSS VCC N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. V CC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS V CC
NOTES: Do not connect any external logic to any pins marked N.C.
26
PRELIMINARY
80960MC
Table 9. 80960MC PGA Pinout -- In Signal Order Signal ADS ALE BADAC BE0 BE1 BE2 BE3 CACHE CLK2 DEN DT/R FAILURE HLDA/HOLDR HOLD/HLDAR IAC/INT0 INT1 INT2/INTR INT3/INTA LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14
NOTE:
Pin D2 D1 C3 H2 G3 J2 K1 F3 B11 L1 J1 K2 D3 C1 C14 C13 A13 C12 B12 A12 B10 C9 A11 A10 B9 A9 C8 A8 B8 A7 B7 C7 A6
Signal LAD15 LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 LAD23 LAD24 LAD25 LAD26 LAD27 LAD28 LAD29 LAD30 LAD31 LOCK N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
Pin B6 A5 A4 B5 A3 C6 B4 B3 B1 B2 C2 E2 E3 E1 F1 G1 F2 H3 D13 D14 E12 E14 F12 F13 F14 G12 G13 G14 H12 H13 H14 J12 J13
Signal N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
Pin J14 K13 K14 L13 L14 M1 M6 M7 M8 M9 M12 M13 M14 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P2 P3 P4 P5 P6 P7 P8
Signal N.C. N.C. N.C. N.C. N.C. READY RESET VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W/R
Pin P9 P10 P11 P12 L2 G2 B13 A1 A14 C4 C10 D12 K12 L3 M2 M5 M11 P1 P14 A2 B14 C5 C11 E11 J3 K3 L12 M3 M4 M10 N1 P13 H1
Do not connect external logic to any pins marked N.C.
PRELIMINARY
27
80960MC
3.3
Package Thermal Specification
The 80960MC is specified for operation when case temperature is within the range 0C to 85C (PGA). Measure case temperature at the top center of the package. Ambient temperature can be calculated from: * * * TJ = TC + P*jc TA = TJ + P*ja TC = TA + P*[ja-jc]
Maximum allowable ambient temperature (TA) permitted without exceeding TC is shown by the graphs in Figure 23, Figure 24 and Figure 25. The curves assume the maximum permitted supply current (ICC ) at each speed, VCC of +5.0 V and a TCASE of +85 C (PGA).
Values for ja and jc for various airflows are given in Table 10 for the PGA package. The PGA's ja can be reduced by adding a heatsink. Table 10. 80960MC PGA Package Thermal Characteristics Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter
Junction-to-Case Case-to-Ambient
0 (0) 2 19 16
50 (0.25) 2 18 15
100 (0.50) 2 17 14
200 (1.01) 2 15 12
400 (2.03) 2 12 9
600 (3.04) 2 10 7
800 (4.06) 2 9 6 J-PIN JA JC J-CAP
(No Heatsink)
Case-to-Ambient
(Omnidirectional Heatsink)
Case-to-Ambient
15
14
13
11
8
6
5
(Unidirectional Heatsink)
NOTES: 1. This table applies to 80960MC PGA plugged into socket or soldered directly to board. 2. JA = JC + CA 3. J-CAP = 4C/W (approx.) J-PIN = 4C/W (inner pins) (approx.) J-PIN = 8C/W (outer pins) (approx.)
28
PRELIMINARY
80960MC
85 80 75 TEMPERATURE (o C) 70 65 60 55 50 45 40 0 100 200 300 400 500 600 700 800 AIRFLOW (ft/min) PGA with no heatsink PGA with omnidirectional heatsink PGA with unidirectional heatsink
Figure 22. 25 MHz Maximum Allowable Ambient Temperature
PRELIMINARY
29
80960MC
4.0
WAVEFORMS
The following figures present waveforms for various transactions on the 80960MC'S local bus: * Figure 23, Non-Burst Read and Write Transactions Without Wait States (pg. 30) * Figure 24, Burst Read and Write Transaction Without Wait States (pg. 31) * Figure 25, Burst Write Transaction with 2, 1, 1, 1 Wait States (pg. 32) * Figure 26, Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States) (pg. 33) * Figure 27, Interrupt Acknowledge Transaction (pg. 34) * Figure 28, Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master) (pg. 35)
Ta CLK2
Td
Tr
Ta
Td
Tr
CLK
LAD31:0
ALE ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 23. Non-Burst Read and Write Transactions Without Wait States
30
PRELIMINARY
80960MC
Ta CLK2
Td
Td
Tr
Ta
Td
Td
Td
Td
Tr
CLK
LAD31:0
ALE ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 24. Burst Read and Write Transaction Without Wait States
PRELIMINARY
31
80960MC
Ta CLK2
Tw
Tw
Td
Tw
Td
Tw
Td
Tw
Td
Tr
CLK
LAD31:0
ALE ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 25. Burst Write Transaction with 2, 1, 1, 1 Wait States
32
PRELIMINARY
80960MC
Ta CLK2
Tw
Td
Td
Td
Td
Tr
Ta
Tw
Td
Tr
CLK
LAD31:0
ALE
ADS
BE3:2
BE1:0
W/R
DT/R
DEN
READY
Figure 26. Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States)
PRELIMINARY
33
80960MC
PREVIOUS CYCLE
INTERRUPT ACKNOWLEDGEMENT CYCLE 1
IDLE (5 BUS STATES)
INTERRUPT ACKNOWLEDGEMENT CYCLE 2
TX
TX
Ta
Td
Tr
TI
TI
TI
TI
TI
Ta
Tw
Td
Tr
CLK2
CLK
INTR
LAD31:0
ADDR
ADDR
VECTOR
ALE ADS
INTA
DT/R
DEN
LOCK
READY
NOTE: INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1. For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted.
Figure 27. Interrupt Acknowledge Transaction
34
PRELIMINARY
80960MC
PBM BUS STATE SBM BUS STATE
Ta Thr
Td Thr
Th Thr
Th Ta
Th Td
Th Tr
Ta Thr
Td Thr
Td Thr
Th Thr
Th Ta
Th Td
Th Td
Th Tr
Ti Ti
CLK LAD31_ LAD0 W/R#
PBM ALE# SBM ALE# READY# SBM HOLDR PBM HOLD PBM HLDA SBM HLDAR
Addr
Data
Addr
Data
Addr
Data
Data
Addr
Data
Data
A4492-01
Figure 28. Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master)
5.0
REVISION HISTORY
No revision history was maintained in earlier revisions of this data sheet. All errata that has been identified to date is incorporated into this revision. The sections significantly changed since the previous revision are: Section Last Rev. Description This is the initial commercial data sheet for the A80960MC.
PRELIMINARY
35
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